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tx if/bba with agc s1m8657 1 introduction s1m8656a/8657 are cdma/amps dual mode if/ baseband ic which is divided into three main parts - if frequency processing, baseband processing , and digital interface. the receiver ic (s1m8656a) and transmitter ic (s1m8657) are provided as a kit. s1m8656a is a receiver ic, installed with a rx agc, baseband converter, baseband analog filter, and a-d converter. it can send a digital baseband signal to the digital baseband ic. the s1m8657 is a transmission-only ic, installed with a tx agc, if frequency converter, analog filter, d-a converter, pll, 8-bit a-d converter for the system monitor, and 3-input analog switch. it connects the digital baseband ic to the rf processing. designed to operate in direction connection with the msm, s1m8656a and s1m8657 are fabricated on the samsung's 0.5um high-speed, high-frequency bicmos processing and can achieve superior high frequency and low power digital operations. its operating voltage is 2.7v ? 3.6v, and operating temperature -30 c ? +85 c. features cdma/amps dual mode agc output signal range : 90db built-in qpsk baseband to if converter built-in tx i and q lpf built in i,q 8-bit dac built-in programmable tx if pll built-in vco for qpsk converter and if conversion built-in 8-bit gp adc with 3-input analog switching built-in 3-line serial port interface (spi) ordering information device package operating temperature + s1m8657x01-e0t0 48-lqfp-0707 -30 to +85 c + S1M8657X01-F0T0 48-bcc-7.0 7.0 -30 to +85 c +: new product 48-bcc-7.0 7.0 48-lqfp-0707
s1m8657 tx if /bba with agc 2 block diagram adc 8 idleb/stb smsb/clk slsb/paon sen fm_mod gpdata txd0-7 tclk tclkb tx_if1 tx_if2 tagc_cont tcxo tx_vco_t1 tx_vco_t2 gpin1 gpin2 gpin3 gpena gpclk fmb/data pdiset pdout lock + x 1/2 div. 90d-psn x tx-pll synthesizer 8 lpf lpf lpf dac dac 3-line serial port interface mode control
tx if/bba with agc s1m8657 3 pin configuration gnd gnd vcc tx_if1 tx_if2 tagc_cont gnd n.c vcc gnd txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 tclk tclkb vddm gnd vcc gpena gpdata gpclk gpin1 gpin2 gpin3 smsb/paon sen fmb/data idleb/stb slsb/clk tcxo lock pdiset pdout gnd vcc fm_mod txvco_t1 txvco_t2 gnd vcc n.c vcc gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 s1m8657
s1m8657 tx if /bba with agc 4 pin description pin name i/o description 1 2 tx_if1 tx_if2 ao outputs differential signal to the if output signal pin. output format is an open-collector. only operates in the cdma/fm talk mode. an external components pull it up using vdd when operation is not allowed. 4 tagc_cont ai dc input for agc gain control. this input is the pdm control signal from the modem, which was converted to a digital signal in the r-c filter. this pin has high impedance when not in operation. 8 n.c - not used in this product. 11 12 13 14 15 16 17 18 txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 di transmit data input pins for transmit 8-bit d/a converter txd7 is the msb. 19 20 tclk tclkb di complementary inputs to transmit d/a converter. 24 gpena di this pin is always on stand-by and is not affected by the sen's pin conditions. if this pin changes from low to high when the tcxo is allowed, gp-adc starts to operate as well as gpdata and gpclk. 25 gpdata do gp-adc conversion data output pin. this pin cannot be operated by the spi but must be operated by the gpena pin. on stand-by, the pin is at low. 26 gpclk do gp-adc conversion data synchronization pulse output pin. this pin cannot be operated by the spi but must be operated by the gpena pin. on stand-by, the pin is at low. 27 28 29 gpin1 gpin2 gpin3 ai 3-analog input terminals. only the input from one of these is input to the gp-adc. the input is selected based on the conditions of the smsb/paon and slsb/clk terminals in the spi restrict mode and on the register value in the spi operating mode. on stand-by, it has high impedance. 30 smsb/paon di sen is the pin for the former bit of the two bits used to select the gp input in low state. this pin executes the paon function when sen=1 and txmode_cont[3] =1 and executes the tx puncture mode when this pin is at low. 31 sen di select pin for the use of the spi bus. if this pin is at high, the spi bus can be used; if low, the spi bus cannot be used but an external control pin can be used.
tx if/bba with agc s1m8657 5 pin description (continued) pin name i/o description 32 fmb/data bi when sen = high, this pin is used as the spi data input pin; when low, it converts to the fmb, the parallel control input. in the parallel control mode, if this pin becomes low, the ic enters fm mode and, if high, cdma mode. 33 idleb/stb di when sen = high, this pin is used as the spi stb(strobe) pin; when low, it converts to idleb, the parallel control input. in the parallel control mode, if this pin becomes low, the ic enters the idle mode, and if high, talk mode. 34 slsb/clk di when sen = high, this pin is used as the spi clk input pin; when low, it converts to the slsb, the parallel control input and becomes the input pin for the latter bit of the two gp input select bit. 35 tcxo ai external tcxo signal input pin, whose input dc potential is 1.5v from only the input bias when not operating. 37 pdiset ao pin determining the charge pump current in the pll, whose operating voltage is 0.64v. the resistance between this pin and gnd determines the charge-pump current, which is r/0.64. 38 pdout ao charge pump current output pin, whose peak current is r/0.64 and 11r/0.64 in the lock mode and acquisition mode, respectively. when not operating, it is at high impedance. 41 fm_mod ao fm modulation fm baseband output signal, which is sent only in the fm talk mode but has high impedance at any other time. 6, 45, 47 vdd power pin for the analog circuit. 3, 5, 7, 22, 39, 44, 48 gnd ground pin for the analog circuit. 21 vddm pin for the digital input/output circuit connected to the modem. 9, 23, 40 vdd_dig digital logic power pin. 10 gnd_dig digital circuit ground pin.
s1m8657 tx if /bba with agc 6 absolute maximum ratings characteristic symbol value power supply v cc -0.5v to 3.6v storage temperature t stg -55 c to +125 c operating temperature t opr -30 c to +85 c electrostatic discharge rating hbm 1500v mm 200v recommended operating conditions characteristic symbol value power supply vcc 2.7v to 3.6v ambient operating temperature t a -30 c to +85 c electrical characteristics (v cc = 3.3v, t a = 25 c) characteristic test conditions symbol min typ max units current consumption cdma idle mode icrx - 20 100 ua current consumption fm idle mode ifrx - 20 100 ua current consumption cdma talk mode agc gain : min ictx1 - 20 30 ma cdma talk mode agc gain : max ictx2 - 40 50 ma current consumption fm talk mode agc gain : min iftx1 - 20 30 ma fm talk mode agc gain : max iftx2 - 40 50 ma logic high input vih v dd -0.4 - - v logic low input vil - - 0.4 v logic high output voh v dd -0.4 - - v logic low output vol - - 0.4 v digital input capacitance cdi - - 5 pf digital output load capacitance txif_out, txif_out/ cdol - - 5 pf tcxo input impedance attach c = 2pf ztcxo 5 - - k w
tx if/bba with agc s1m8657 7 electrical characteristics (continued) characteristic test conditions symbol min typ max units tx if load resistance txif_out, txif_out/, differential rif - 1 - k w tx if output capacitance txif_out, txif_out/, differential cif - - 2 pf tx if output impedance txif_out, txif_out/, differential zif 30 - - k w vco input resistance tx vco_t1, tx vco_t2 rvco 1.8 2 2.2 k w vco input capacitance tx vco_t1, tx vco_t2 cvco - - 1.5 pf tx agc gain control input impedance tagc_cont zagc 30 80 - k w
s1m8657 tx if /bba with agc 8 electrical characteristics characteristic test conditions symbol min typ max units cdma performance output center freq. maximum operating if frequency ftr - - 300 mhz minimum output power output power when full scale i and q data are input to the dac at minimum agc gain minp - - -83.2 dbm maximum output power output power when full scale i and q data are input to the dac at maximum agc gain maxp 0 - - dbm agc control voltage range input voltage examination that responds to the control input when input 15k w resistance is series-connected to the tagc_cont vcon 0.1 2.4 v agc gain slope linear control range examination that measures the gain difference between control voltages, 1.0v and 2.0v. g slp 33 45 53 db/v agc gain slope linearity examines how far the gain change between control voltages 1v ? 2v is from the ideal g lin -3 - 3 db in-band spurious free dynamic range spurious measurement between @1khz ? @630khz that appears at the if output when two in-band 0.5f/s signal are input to the dac i spur 35 - - dbc edge-band spurious free dynamic range spurious measurement between @630khz ? @1.98mhz that appears at the if output when two in-band 0.5f/s signal are input to the dac. e spur 35 - - dbc out-band spurious free dynamic range spurious measurement above @1.98mhz that appears at the if output when two in- band 0.5f/s signal are input the dac o spur 57 - - dbc carrier feed through examines the carrier feed through when i and q single-tone f/s in-band cdma spread spectrum data are input. cf 28 dbc spurious free dynamic range: if harmonics examines the if harmonics in the 1.23mhz range after i and q single tone f/s data are input. e sfdr 20 - - dbc o sfdr 9.5 - - dbc snr, noise band1 sets the control voltage so that agc if outputs -83.2dbm ? 0.8dbm when i and q single tone f/s data are input. converts the noise within @100khz ? @1.98mhz to dbc/hz. snr 1a 104 - - dbc/hz
tx if/bba with agc s1m8657 9 electrical characteristics (continued) characteristic test conditions symbol min typ max units cdma performance snr, noise band2 sets the control voltage so that agc if outputs -83.2dbm ? 0.8dbm when i and q single tone f/s data are input. converts the noise within @1.98mhz ? @44mhz to dbc/hz. snr 2a 116 - - dbc/hz acpr band1 examines the difference between the power in the @1.23mhz band and the noise power in the 30khz band after is-98 specified cdma data is input. acpr1 52.1 - - db/ 30khz acpr band2 examines the difference between the power in the @1.23mhz band and the noise power at 1.98mhz in the 30khz band after is-98 specified cdma data is input. acpr2 68.1 - - db/ 30khz upper-side-band suppression examines the i and q gain and phase error. examines the usb suppression ratio after i and q single-tone f/s data is input. usb 25 - - dbc amplitude flatness examines the change in if amplitude between @1khz ? @630khz. af - - 1 dbpp tx puncturing settling time examines the on-off settling time of the tx block when paon=low in the talk mode. st - - 6 us fm performance minimum output power output when full scale data is input to the dac at minimum agc gain. min pf - - -50 dbm maximum output power output when full scale data is input to the dac at maximum agc gain. max pf -3 - - dbm agc control voltage range examines the input voltage responding to the control input when 15k w resistance is series-connected to tagc_cont. v cont 0.1 v cc - 0.1 v agc gain slope examines the gain difference between control voltages 1.0 v and 2.0v to examine the linear control band. g slp 33 45 53 db/v agc gain slope inearity examines if the gain change between control voltages 1v ? 2v is not ideal. g lin -3 - 3 db if snr noise band1 examines the noise density between @100khz ? @44mhz when single-tone f/s data is input. this characteristic generally depends on the vco phase noise characteristics. snr f1 110 - - dbc/hz maximum spurious content: examines the harmonics at the if when single -tone f/s data is input. e sfdr 20 - - dbc if harmonics o sfdr 9.5 - - dbc
s1m8657 tx if /bba with agc 10 electrical characteristics (continued) characteristic test conditions symbol min typ max units snr, noise band1 sets the control voltage so that agc if outputs -83.2dbm ? 0.8dbm when i and q single tone f/s data are input. converts the noise within @100khz ? @1.98mhz to dbc/hz. snr 1a 104 - - dbc/hz snr, noise band2 sets the control voltage so that agc if outputs -83.2dbm ? 0.8dbm when i and q single tone f/s data are input. converts the noise within @1.98mhz - @ 44mhz to dbc/hz. snr 2a 116 - - dbc/hz acpr band1 examines the difference between the power in the @1.23mhz band and the noise power in the 30khz band after is-98 specified cdma data is input. acpr1 52.1 - - db/ 30khz acpr band2 examines the difference between the power in the @1.23mhz band and the noise power at 1.98mhz in the 30khz band after is-98 specified cdma data is input. acpr2 68.1 - - db/ 30khz upper-side-band suppression examines the i and q gain and phase error. examines the usb suppression ratio after i and q single-tone f/s data is input. usb 25 - - dbc tcxo/vco/pll performance tcxo input frequency f tcxo - 19.68 25 mhz tcxo input level l tcxo - 0.5 2.0 vpp tx vco frequency f tvco - - 500 mhz lock mode current rset = 39k w lc 14 16 18 ua acquisition mode current rset = 39k w ac 140 160 180 ua reference spur depend on loop bandwidth rs - - -70 dbc max. acquisition mode current rac 1 - - ma acquisition to lock mode transition range wld - - 1 khz charge pump compliance voltage io=16ua vchg 0.4 - v cc - 0.4 v phase detector unlock threshold during fm ulfm - - 12 khz
tx if/bba with agc s1m8657 11 timing diagrams tclk period: 203.4ns rising time: 3 -12ns tclk falling time: 3 - 12ns q-data q-data i-data high time: 101.7ns data setup to tclk transition: 20ns data hold after tclk transition: > 3ns tclk to tclkb phase delay: < 1.2ns tclkb txd[7:0] low time: 101.7ns 90% 10% i-data i-data q-data figure 1. cdma transmit dac timing tclk period: 8.33us rising time: 3 - 12ns tclk q-data high time: 4.17us data setup to tclk transition: > 20ns data hold after tclk transition: > 3ns tclk to tclkb phase delay: < 1.2ns tclkb txd[7:0] low time: 4.17us falling time: 3 - 12ns 90% 10% q-data q-data figure 2. fm transmit dac timing
s1m8657 tx if /bba with agc 12 clock period: 2.44us rising time: 3 - 12ns falling time: 3 - 12ns high time: 1.22us low time: 1.22us gpena high to conversion end: <40us d7 d6 d5 d4 d3 d2 d1 d0 gpclk gpena gpdata * all timing specifications is based on gpclk=410khz gpena high to gpclk: 17us gpdata valid before gpclk rising edge: 50ns - 780ns gpdata valid after gpclk falling edge: 50ns 90% 10% figure 3. gp-adc timing clock period: 0.6 - 10us clock duty cycle: 35 - 65% clk stb n+1 data bit set-up time: > 50ns valid data bit (n) data line hold time: 50 - 200ns stb line setup time: 50ns all data transitions happen while clk=low clcok n stb line hold time: 50 - 200ns data clcok n+1 clcok n+2 valid data bit (n+1) valid data bit (n+2) figure 4. 3-line serial port interface timing
tx if/bba with agc s1m8657 13 functional description s1m8657, a functional block used in tx signal processing, is located between the rf pre-block and modem. this product converts the digital i and q baseband signals sent by the modem to their corresponding analog signals and moves their frequencies to the if mid-frequency, where their output levels are controlled. then, the differential if signal is output. because it has the built-in spi bus i/f and parallel mode control, it is compatible to the existing bba2.0. the programmable tx pll is used to generate the precise if mid-frequency. here, the vco, which oscillates at twice the if frequency, and qpsk modulator moves the if frequency from the baseband. the agc, connected to the tx if saw filter, amplifies or reduces the if signal level, required by the cdma system, at a certain point. its gain is controlled by the dc voltage in the tagc_cont and its output level range is approx. 90db. the gp-adc possessing a switch that can select from three independent inputs is as system monitor a-d converter, which senses the battery type, remaining battery amount, and temperature. various inputs and conditions for this converter can be set via the spi bus. moreover, it can use the same bba 2.0 conditions and parallel control inputs. s1m8657 uses a 0.5um bicmos, equipped with high-frequency bipolar and low power standardized cmos logic, to operate safely in the low power range, consisting of power voltage between 2.7v ? 3.6v and operating temperature between -30 c ? +85 c. cdma transmit signal path s1m8657 is a transmit circuit, installed with pll, gp-adc and mode change switch and serial i/f. the transmit circuit has the tx agc, an automatic gain controller, and baseband lpf and d-a converter as well as a vco and mixer etc. the cdma if output signal is a differential signal modulated to 1.23 mhz spread-spectrum for cdma with a normal mid-frequency at 130.38mhz. the mid-frequencies are set based on the time constants of the components involved with the external vco and tx pll. tx agc , connected to both the if saw filter and matching component in the if-rf converter output located in the rf block, amplifies or reduces the signal according to the signal size. it takes its orders from the modem chip when it sets the appropriate power level as required by the cdma system. gain is controlled by applying a dc voltage to the tagc_cont pin. the applied dc is produced when the pdm signal, generated as a control signal in the modem, passes through the r-c filter. the control band of this agc is approx. 90db. the qpsk modulator mixes and adds the i-q baseband signals, output from the dac-lpf, with the i-lo and q-lo signals, respectively, to generate the qpsk signal, which is sent to the agc which in turn sends the differential if to the rf signal processing block. the lo(local oscillator) signal is generated by the internal oscillating components, externally connected tank coil, and varactor, and the externally independent pll device is used to generate its exact oscillation mid-frequency. fm transmit signal path because the fm modulation in the s1m8657 fm circuit differs entirely from the qpsk, the fm transmit signal path is very different. the transmit circuit includes an automatic gain controller, tx agc, baseband lpf, d-a converter as well as the vco and mixer, which are all the essential blocks as included in the cdma. the fm signal is a 12khz modulated signal, with normal mid-frequency of 130.38mhz. these mid-frequencies are determined by the time constants of the components involved with the external vco and tx pll. tx agc , connected to both the if saw filter and matching component in the if-rf converter output located in the rf block, amplifies or reduces the signal according to the signal size. it takes its orders from the modem chip when it sets the appropriate power level as required by the cdma system. gain is controlled by applying a dc voltage to the tagc_cont pin. the applied dc is produced when the pdm signal, generated as a control signal in the modem, passes through the r-c filter. the control band of this agc is approx. 90db. only the analog q baseband signal output by the q- path dac-lpf is used in fm modulation and directly connected to the external varactor baseband to change the lo frequency to generate the fm modulation signal. this signal is sent to the agc, which sends the differential if to the rf signal processing block.
s1m8657 tx if /bba with agc 14 serial port interface(spi) s1m8657 is equipped with the serial i/f. all internal functions can be controlled through a common bus using an external controller. the serial i/f can be used by setting pin 31(sen) high, the pin which permits/ not permit the spi. if the sen becomes low, the spi cannot be used and the bba must be used in the existing bba 2.0 mode. (all the internal registers are default, which makes the register have the same characteristic as bba 2.0) here, the modem is the master and bba the slave. each pin which uses the spi bus has the following common functions. the stb(strobe) for the serial bus start signal is used to reset serial data transmission. this pin is used with the idleb function in manual mode and designated the idlb/stb pin. serial bus data is used for the bidirection data input /output at serial data transmission. this pin is used with the fmb function in parallel mode and designated the fmb/data pin. because it is an open drain type pin, it requires the pull-up resistance of approx. 8k w . serial bus clk is used to synchronize the data input/output at serial data transmission. this pin is used with the sleepb function in manual mode and designated the sleepb/clk pin. the sen(pin31) pins decide on whether the product will used the spi bus or parallel control inputs; if is in low, then the pins the parallel control input functions, idleb, fmb, and sleepb, but if in high these pins execute the spi bus functions, stb, data, and clk. the maximum data transmission (clock frequency) is 1.53mhz. this product does not require any external time constants in the internal register because it can use the internal reset function. fig. 5 shows the serial connection. slot stb/idleb clk/sleepb data/fmb sen smsb/paon stb/idleb clk/slsb data/fmb sen s1m8656a s1m8657 sleepb sbst/adc_ena sbck/adc_clk sbdt/adc_data paon modem v dd 8k w figure 5. serial bus connection
tx if/bba with agc s1m8657 15 serial port interface operation the modem , the master, controls slaves such as s1m8657 using the spi bus. the stb falling edge indicates the start of the serial i/f data transmission. the stb becomes high to mark the end of the data transmission. (data sent after the stb turns high are not valid.) serial line data is captured and stored as soon as the bba or the modem places the clock on the falling edge. the spi 3-line must remain high for at least 1-clock cycle in order to sent new data. the msb always outputs the data line data. after 9-clocks, which is required to send data, the data line driver opens the data line, at which time the data line becomes high because of the external pull-up resistance. serial data transfer format s1m8656a and s1m8657 are all slave devices with the spi bus. what differentiate them from one another is their different device ids. each company has its own characteristic spi bus configuration , but normally the 3-line bus is most often used and sometimes the 2-line bus such as the iic bus. figure 6. shows the serial data transfer format. mode=01 dummy 1= master read master drive slave address dummy master drive register address slave drive data dummy 0 = master write master drive register address master drive data dummy dummy end bit start bit stb clk data d5 0 1 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 6. serial data transfer format (1) the first 2-bits are for transmission only and this product must send '01'.(others are not permitted.) (2) the following 6-bit data specifies the slave device, which is connected to the spi bus and has its own id. (3) the following 1-bit is a dummy bit, which marks the end of the 8-bit data transmission and the beginning of the next data to be sent. (4) the following 1-bit decides on whether the master will drive the data line or the slave will. if this bit is '1', the master will drive , but if '0' the slave will drive the data line. (5) the following 7-bit data is the register address of the specified slave device; the 7-bits for an address allows 128 register addresses for slaves. (6) the following high 1-bit data is a dummy data. (7) the following 8-bit data is the data in the device to be driven. (8) the following 1-bit data is a dummy data, which marks the end of the 8-bit data transmission and beginning of the next data to be sent. (9) the following 1-bit decides on whether the master wil l drive the data line or the slave will. if this bit is '1', the master will drive , but if '0' the slave will drive the data line.
s1m8657 tx if /bba with agc 16 (10) the following 7-bit data is the register address of the specified slave device. (11) the following high 1-bit data is a dummy data. (12) the following 8-bit data is the data in the device to be driven. (continuos data transmission such as this can be ended with a 1-byte transmission or can be read/written repeatedly.) (13) after the last data is sent, the data line opens and becomes high; (14) clk continues for half the 1-clock cycle and then becomes high; (15) stb becomes high as soon as the clock becomes high and this marks the end of data transmission.
tx if/bba with agc s1m8657 17 modes of operation s1m8657 can be controlled by parallel control mode or by spi bus. the analog switch , an existing external component, in the ic an be also controlled through separate specified parallel inputs or by spi. the modes of operation can be formed by parallel inputs such as fmb, idleb, and paon, or by related spi registers, as shown in table 1. table 1. mode control in the parallel mode control mode fmb idleb paon cdma talk h h h cdma idle h l x fm talk l h h fm idle l l x tx puncture (spi only) x h l the modem in cdma transmit mode operates the i and q dac in s1m8657, which then outputs the cdma spread-spectrum with tx if mid-frequency. all the circuits in s1m8657 are stopped in cdma receive mode (idle). the modem only operates q-dac in the fm transmit mode (talk). besides this, all cdma related circuits are stopped. the signal for fm modulation passes through the q-fm-lpf (fm-mod) output pin to come out. all circuits in s1m8657 are stopped in fm receive only mode (idle). because tx puncture mode can only be controlled through the spi bus, it turns on and off the blocks related to the intervals with no data. by doing so, it minimizes the consumption current. the spi registers related to this feature are controlled by setting paon = low, sen = high, idleb = high. tx phase locked loop s1m8657 has a built-in programmable pll which can determine the if mid-frequency. if the spi bus is not used, the default value in the built-in register must be used; the tx if frequency is 130.38mhz when tcxo = 19.68mhz. the block diagram of the pll is shown in figure 7. the pll is composed of the vco, r-divider, n- divider, and phase detector, while the loop filter and vco components are outside s1m8657. the divide ratios in the pll r and n counters can be programmed through the spi bus. these can change the phase comparison frequency. the n-counter is composed of a 9-bit a-counter and 4-bit b-counter and 8/9 or 16/17 dual- modulus prescaler.
s1m8657 tx if /bba with agc 18 pllr0[7:0] pllr1[1:0] plln0[3:0] plln0[7:4] plln1[4:0] pll_mode[6] pllr1[7:5] pll_mode[4:3] n counter to mixer tx_vco_t1 tx_vco_t2 tcxo pdiset pdout lock divide by 2 tx vco prescaler p or p+1 a-counter b-counter phase detector r-counter lock detector charge pump figure 7. tx pll synthesizer block diagram
tx if/bba with agc s1m8657 19 the a and b-counter divide ratios can be changed by programming the pllno and plln1 among the spi registers. they pass through the vco internal output, txvco_out, and are input to the prescaler, and the prescaler outputs are input to a and b-counters. if the b-counter is not "0", the prescaler divides by p+1(division ratio of 9 or 17 ); if b-counter is "0", the prescaler divides by p(division ratio 8 or 16). if a-counter becomes "0", n-counter is reset. if a-counter output becomes fv, this becomes the comparison input for the pd (phase comparator). r-counter can be changed by programming pllr0 and pllr1 of the spi registers. as a 10-bit divider, r-counter divides tcxo, which is then used as the reference input for the pd. 9- bit a-counter plln1[4:0] plln0[7:4] plln0[3:0] 4-bit b-counter msb lsb figure 8. map of n counter pllr0[7:0] pllr1[1:0] msb lsb figure 9. map of r counter the n-counter divide ratio (n) changes according to the prescaler value and is determined by the following equation. n = p a + b, where a 512, 0 b (p-1), and b < a. the prescaler can use plln1[7] to select from either 8/9 or 16/17, the reference value being 16/17. if this bit becomes "0", 8/9 is chosen as the prescaler divide ratio. n-counter, composed of the 9-bit a-counter and 4bit b-counter, lowers the vco frequency and sends it to the pd. pll equation : n-counter divide ratio n = f vco /f pd a-counter divide ratio a = int(n/p), a 512. the value of a written into plln1 and plln0 as shown in figure 8 is a binary value for a-1. for example, the reference values, plln1[4:0]=00000 and plln0[7:4]=1100, are decimal, 12, and a is for 13. the b-counter can be programmed with plln0[3:0]. b = n - p a, 0 b 15, p=16 the reference value for a and b-counter (a=13, b=4) makes the vco oscillating frequency equal to 260.76 mhz when tcxo is at 19.68mhz, and pd phase comparison frequency becomes 1.23mhz. the 10-bit r-counter can be programmed using the spi registers, pllr0 and pllr1. the r-counter makes the f r input signal for pd based on the tcxo reference signal. r-counter divide ratio r = f ref /f pd the r-counter value set based on pllr0 and pllr1 is for r-1; for example, when pllr0 = 00001111 and pllr1=00, decimal value is 15, but it is r-1, real value r is 16.
s1m8657 tx if /bba with agc 20 [order of divide ratio calculation] vco = 260.76mhz, tcxo = 19.68mhz, phase detect frequency = 1.23mhz, prescaler = 16 1) determine the value of n : n = f vco /f pd = 260.76mhz/1.23mhz = 212 2) determine the value of a : a = int(n/p) = int(212/16) = 13 when this value is set in the register, the value of a-1(12) must be placed. binary value is 000001100. 3) determine the value of b : b = n - p a = 121 - 16 13 = 4 4) determine the value of r : r = f ref /f pd = 19.68mhz/1.23mhz = 16 the r register value is r-1 so 15 must be written. binary value is 0000001111. the external pdiset resistance determines the charge pump from pdout. this resistance determines the current flowing between pdiset and gnd as follows. io = rset/0.64v io is the charge-pump current when the pll is locked. if the resistance is 39k w , io becomes 16ua. the charge-pump current is classified into lock mode current and acquisition mode current to quickly stabilize the un-locked ic. the charge-pump current of the acquistion mode flows 10 times faster than that of the lock mode, thus providing faster stability. although the lock-acquisition current can be changed from one to the other, the spi pll_mode [4:3] register value can be used to permanently set the charge-pump current as either acquisition mode current or lock mode current. however, the type of current to be set should be carefully decided based on the amount of surrounding noise flowing into vco. the charge-pump polarity can be change with pllr1[4] to respond to the various conditions of the capacitor, whose value can be changed "+' or "-" for the varactor signal, according to how the vco is used. a lock pin has been prepared to indicate that lock has occurred because the tx frequency has entered the set band. this pin can be used to select from either the open-drain output or cmos output. if the open_drain output is selected, an external 10k w pull up resistance is required. pll_mode[6] can be set to select the output type. lock -unlock states can be determined by counting how many times the phase difference between the signal in the ic and the reference signal matches within the set phase difference band. two criteria which can be used to detemine the lock are the phase difference band and the frequency of phase match during a set period. here the user can select the frequency of phase match, the purpose of which is to determine whether or not the lock is a stable lock or a temporary lock condition. namely, the lock condition ,when there are many phase matches, is a very stable condition, but it requires time. the phase difference here refers to the phase difference between the n-counter output fv and r-counter output f r . whether or not to cancel the lock condition can be decided by determining how many times 2 phase differences fall within the set range within a specified duration. pllr1[7:5] spi register is used to set the phase match or unmatch frequency limit. here , this limit is called the lock-length, which is determined as follows: f r is the reference frequency in the phase comparator. f r = f tcxo /r, f tcxo is the basic tcxo frequency, r is the divide ratio for the basic tcxo frequency(r-counter) fv is the vco dividing frequency which is compared to the reference frequency in the phase comparator. fv = (f vco + f error )/n, where f vco is the vco basic frequency and f error is the allowable maximum frequency range. based on the above equation, the number of pd pulses required for the vco frequency in a set band is n pd = 2 t tcxo /(1/f r - 1/f v ), t tcxo is the period of the tcxo basic frequency. the number of tcxo pulses for the vco frequency in a set range is n tcxo = r n pd where, lock-length m = log 2 (n tcxo ) - 13 lock counter length is 2 (m+13) .
tx if/bba with agc s1m8657 21 the m in binary can be set by changing the pllr1[7:5] register value. and normally, f error is designed to the limit of 1khz. [an example of a lock length design ] f vco = 260.76mhz; f tcxo = 19.68mhz; f error = 1khz; r = 16, n = 212 f r = f tcxo /r = 19.68mhz/16 = 1.23mhz fv = (f vco + f error )/n = 1230004.71698 n pd = 2 t tcxo /(1/f r - 1/fv) = 32600 n tcxo = r n pd = 16 32600 = 521600 m = roundup{log 2 (n tcxo )} - 13 = roundup(18.9926) - 13 = 6 therefore. lock detector length is 2 19 tcxo . general purpose adc the gp-adc for the system monitor has a built-in 3-input switch serial 8-bit a-d converter and is used generally used to sense the temperature, and battery amount and type. the gp-adc can be controlled by the following methods. ? parallel control as in the existing s1m8653b when the spi is not used and sen = low. gpena, gpdata, and gpclk must be used. ? basic and enhanced modes exist with spi use when sen = high : controlled through the spi register and gpena in the basic mode(txmode_cont[0] = low), and can output through either the spi register or gpdata and gpclk pins. : controlled according to the contents in the gpadc_mode[7:0] in the enhanced mode(txmode_cont[0] = high). general purpose adc operation without spi (sen = low) when sen = low, the serial bus(spi bus) is not used. in such a case, gp-adc is controlled through slsb, smsb, gpena, gpdata and gpclk provided from external pins or data must be sent. under these conditions, the gp-adc is reset at the rising edge of gpena from the modem and starts the conversion. the converted digital code is synchronized to the continuous 9 gpclk and sent to the modem. to start a new gp- adc conversion, gpena must be at low. input range or signal are selected based on the smsb/paon and slsb/clk states, as shown in table 2. table 2. input and range select (sen = low) smsb slsb gpin vin mid input range lsb/step zin 0 0 gpin1 0.75v 0.5v 2mv 0 1 gpin1 1.5v 2v 8mv 1 0 gpin2 1.5v 2v 8mv 1 1 gpin3 1.5v 2v 8mv
s1m8657 tx if /bba with agc 22 general purpose adc enhanced-mode operation using spi (sen = high, txmode_cont[0] = high) when sen = high the spi bus can be used. the gp-adc operates in the basic mode or enhanced mode. if the txmode_cont[0] is "1", it operates in the enhanced mode and the spi registers control the input selection, clock frequency and input range. the basic setting is the basic mode. if txmode_cont[0] = "1" in the basic mode, the gp-adc operates in the enhanced mode. if all gp-adc related controls and input/output function are conducted through the spi bus, the gp-adc only outputs the spi input/output. gpena can also drive gp-adc; in this case, gpdata and gpclk are output and save at the same time in the spi register, gpadc_rslt[7:0], except that nothing can be input to the input select pins , smsb/paon and slsb/clk. it's simpler to think that in this mode the spi registers perform the roles of what the parallel control pins did in the existing s1m8653b if gpena and txmode_cont[7] = high, gp-adc starts the conversion. moreover, for a new conversion, gpena and txmode_cont[7] must be left at low, and restart begins at the rising edge of when they become high. while conversion is going on, gp-adc cannot receive any signals. gpadc_rslt[7:0], which has the gp-adc conversion value, maintains its previous value until the end of the new conversion. table 3. enhanced-mode register definition gp mode clock divide ratio input range input select gpadc_mode[7:0] d7 d6 d5 d4 d3 d2 d1 d0 default 1 0 0 1 0 0 0 0 table 4. enhanced-mode analog mux gpadc_mode[1:0] input select gpadc_mode[1:0] input select 00 gpin1 10 gpin2 01 reserved 11 gpin3
tx if/bba with agc s1m8657 23 table 5. enhanced-mode input range selection gpadcv[5:2] vin(mid) input range lsb mv/step zin 0000 1.0v 1v 4 0001 2.0v 1v 4 0010 1.5v 2v 8 0011 1.5v 2v 8 0100 0.75v 0.5v 2 0101 1.5v 2v 8 0110 1.5v 2v 8 0111 1.5v 2v 8 1000 0.5v 1v 4 1001 1.0v 2v 8 1010 1.25v 0.5v 2 1011 1.5v 1v 4 1100 2.0v 2v 8 1101 1.5v 0.5v 2 1110 1.75v 0.5v 2 1111 2.0v 0.5v 2 gp-adc enhanced mode inputs are shown in table 5. the ic input impedance is always kept high to reduce the loading effect of the input impedance. however, if the external input divider impedance is very large, the parasitic capacitor cannot charge or discharge quickly enough, generating a high speed conversion error. therefore, it is best to use a low resistance at the input terminal. the lsb step is the difference between the input voltages that generate two codes, respectively. this is shown in table 5. the gp-adc needs the clock for conversion. this clock self-divides and uses tcxo and influences the conversion time. although a 412khz clock was used in s1m8653b, this ic can select from clock speeds between 308khz ? 1.23 mhz, as shown in table 6, according to the contents in spi register gpadc_mode[6:7]. the recommended clock speed is between 410khz ? 615khz. table 6. gp-adc clock divide ratio gpadc_mode[7:6] clock divide ratio system clock(tcxo = 19.68mhz) 00 16 1.23mhz 01 32 615khz 10 48 410khz 11 64 308khz
s1m8657 tx if /bba with agc 24 general purpose adc basic-mode operation using spi (sen = high, txmode_cont[0] = low) spi can be used when sen= high. the gp-adc operates in the basic mode. under these circumstances, gp- adc is under the control of the spi registers. the results of conversion can be output to not only the spi register gpadc_rslt[7:0] but also to gpdata and gpclk. when the basic mode turns on and spi starts, they are automatically set. if the txmode_cont[0] is "0" and all gp-adc related controls and input/output function are conducted through the spi bus, the gp-adc only outputs the spi input/output. gpena can also drive gp-adc; in this case, gpdata and gpclk are output and save at the same time in the spi register, gpadc_rslt[7:0]. in this mode, mode_cont[6:5] register holds the parallel input pins, smsb/paon and slsb/clk. if gpena changes from low to high or gpdac_mode[7] register from "0" to "1", the gp-adc stars the conversion. essentially these indicate the start of conversion in basic mode. for a new conversion, these gpena and gdac_mode[7] must be left at low state and intialization starts at the rising edge of when they become high. while conversion is going on, gp-adc cannot receive any signals. gpadc_rslt[7:0], which has the gp-adc conversion value, maintains its previous value until the end of the new conversion. table 7. gp-adc range select in basic mode gpadc_mode[4] txnode_cont[6:5] vin mid input range lsb(mv) gpadc input zin 0 00 1.0 1.0 4 gpin1 0 01 2.0 1.0 4 gpin1 0 10 1.5 2.0 8 gpin2 0 11 1.5 2.0 8 gpin3 1 00 0.75 0.5 2 gpin1 1 01 1.5 2.0 8 gpin1 1 10 1.5 2.0 8 gpin2 1 11 1.5 2.0 8 gpin3 gp-adc can select from various input range as well as resolution value for each mid-voltage and lsb. it has a built-in input switch, which allows for easy connection with the input sensor. all programmable options are set by spi registers txmode_cont[6:5] and goadc_mode[4]. general purpose adc conversion time gp-adc conversion time is determined based on the tcxo and gp-adc clock divide ratio in the spi register gpadc_mode[7:6]. gp-adc needs a total of 6 gpclk cycles from its restart to start of data sampling; the required adc conversion time is 8 and 1/2 gpclk cycles. a total of 14.5 gpclk cycles are used. table 8. maximum conversion time gpadc_mode[7:6] units 00 01 10 11 tcxo frequency mhz 19.68 19.68 19.68 19.68 divide ratio 16 32 48 64 conversion time us, max 11.79 23.58 35.37 47.17
tx if/bba with agc s1m8657 25 control registers register name address r/w default vale description reset 0x00 w - reset. resets s1m8657 and all the register values are returned to their original value. spi_id 0x01 r 0x2a spi_id. all slaves have an independent id, which is used to distinguish the devices connected to the spi bus and to send data to the desired device. plln0 0x02 r/w 0xc4 plln0. determines the divide ratio needed in the pll divider. plln1 0x03 r/w 0x80 plln1. determines the divide ratio needed in the pll divider. pllr0 0x04 r/w 0x0f pllr0. determines the divide ratio needed in the pll divider. pllr1 0x05 r/w 0xd0 pllr1. determines the divide ratio needed in the pll divider. pll_mode 0x06 r/w 0x00 pll_mode not applied 0x07 not used not applied 0x08 not used not applied 0x09 not used txmode_ctl 0x0a r/w 0x02 txmode_ctl sets the transmission mode gpadc_result 0x0b r - gpadc_result gp-data storage. gpadc_mode 0x0c r/w 0x90 gpadc_mode sets the gp-adc. on_off 0x0e r/w 0x08 on_off decides on whether to operate the functional block to be used in tx puncture. to use this register, paon must be low and talk mode must be in place. reserved 0x10 absolutely not used. reserved 0x11 absolutely not used.
s1m8657 tx if /bba with agc 26 description of register address name type bits description 00 reset w - this is used like a command and if this address is accessed, all register values are restored to their original set value. 01 spi_id r [5:0] this id number must be used to use the registers as s1m8657 in this ic. spi_id = 2ah 02 plln0 [7:0] r/w [7:4] pllac[3:0]. default = 1100. refers to the lower 4-bit in the 9-bit a-counter. remember that the total 9-bit value refers to the a-1 value. [3:0] pllbc[3:0]. default = 0100. register that sets the 4-bit b-counter. 03 plln1 [7:0] r/w [7] psc_mode, default = 1. sets the prescaler dual mode. 1: p = 16 mode, with divide ratio of 16 or 17. 0: p = 8 mode, with divide ratio of 8 or 9. [6:5] default = 00 absolutely not used. [4:0] pllac[8:4]. default = 00000. refers to the upper 5-bit in the 9-bit a-counter. remember that the total 9-bit value refers to the a-1 value. 04 pllr0 [7:0] r/w [7:0] pllrc[7:0]. default = 00001111. refers to the lower 8-bit in the 10-bit a-counter. remember that the total 10-bit value refers to the a-1 value. 05 pllr1 [7:0] r/w [7:5] lock_len. default = 110. lock output set register sets the lock output by detemining the time cut-line for level of pll & vco stabilization phases must match duringtcxo*2 (m+13) for lock. [4] pd_mode. default = 1 decides the polarity of the phase comparator gain (+ or -1). 0: negative vco gain (-kv) 1: normal operation. [3:2] default = 00, absolutely not used. [1:0] pllrc[9:8]. default = 00. refers to the upper 2-bit in the 10-bit r-counter. remember that the total 10-bit value refers to the r-1 value. 06 pll_mode r/w [7] default = 0. absolutely not used. [6] lock_mode. default = 0. assigns the lock output form, the lock detector output. 1: standard cmos output 0: requires an external pull up register because of the open drain output. [5] default = 0 absolutely not used.
tx if/bba with agc s1m8657 27 description of register (continued) address name type bits description [4:3] chg_pmp. default = 00. sets the charge-pump mode. 00: normal operation( separates the current amount for lock- aquisition mode.) 01: not used 10: always operates it with 10x acquisition current. 11: always operates it with 1x lock current. [2:0] default = 000, reserved 0a txmode_ cont [7:0] r/w [7] gpadc_on. default = 0. gp-adc conversion start command register. this bit must be on stand-by as "0" to start a new conversion. 1: resets gpadc and starts conversion. 0: gpadc conversion stand-by. [6] gp_smsb. default = 0 upper 1-bit of the 2-bit input for selecting input switch. 1: smsb is "1". 0: smsb is "0". [5] gp_slsb. default = 0 lower 1-bit of the 2-bit input for selecting the input switch. 1: slsb is "1". 0: slsb is "0". [4] cdma_mode. default = 0(fm) replaces the existing fmb pin function. 1: sets cdma mode. 0: sets fm mode. [3] idle_mode. default = 0(idle) replaces the existing idleb pin function. 1: talk mode. 0: idle mode. [2] default = 0, not used. [1] default = 1, not used. [0] gpenh. default = 0 select bit for enhanced mode or basic mode in the gp-adc mode 1: gpadc is set to enhanced mode. 0: gpadc is set to basic mode. 0b gpadc_rslt r [7:0] saves the most recent conversion value as read-only.
s1m8657 tx if /bba with agc 28 description of register ( continued) address name type bits description 0c gpadc_mode r/w [7:6] gpadc_clk. default = 10. sets the internal clock divide ratio for gp-adc conversion. 00: tcxo/16, gpadc clock=1.23mhz with tcxo=19.68mhz 01: tcxo/32, gpadc clock=615khz with tcxo=19.68mhz 10: tcxo/48, gpadc clock=410khz with tcxo=19.68mhz 11: tcxo/64, gpadc clock=308khz with tcxo=19.68mhz [5:2] gpadc_ran. default = 0100 gp-adc input range and precision selection. (txmode_cont[0] = 0) [1:0] gpadc_in. default = 00. selects one of the 3-inputs. 00: in1, 01: not used, 10: in2, 11: in3 gpadcv[5:2] vin mid input range lsb mv/step zin 0000 1.0 1 4 0001 2.0 1 4 0010 1.5 2 8 0011 1.5 2 8 0100 0.75 0.5 2 0101 1.5 2 8 0110 1.5 2 8 0111 1.5 2 8 1000 0.5 1 4 1001 1.0 2 8 1010 1.25 0.5 2 1011 1.5 1 4 1100 2.0 2 8 1101 1.5 0.5 2 1110 1.75 0.5 2 1111 2.0 0.5 2
tx if/bba with agc s1m8657 29 description of register( continued) address name type bits description 0e tx_pwr r/w [7] txdac_pwr. default = 0 stops the tx-dac. 1: txdac stop. 0: txdac operation. this register is valid only when the paon pin is at low. [6] txflt_pwr. default = 0 stops tx-cdma/fm filter. 1: tx filter stop. 0: tx filter operate. [5] upmix_pwr. default = 0 stops tx-vco, mixer, and quad_gen. *advantageous in terms of set-up time when not used. 1: tx vco, mixer, and quad_gen stop. 0: tx vco, mixer, and quad_gen operate. [4] txagc_pwr. default = 0 stops tx-agc. 1: txagc stop. 0: txagc operate. [3] txpath_pwr. default = 1 stops tx-agc. 1: txagc stop. 0: txagc operate. [2] txpll_pwr. default = 0 stops the pll. *do not use when there is a problem with set-up time. 1: tx_pll stop. 0: tx_pll operate. [1] txmix_pwr. default = 0 stops tx-mixer and quad_gen. *recommend using this bit rather than upmix_pwr bit. 1: tx mixer and quad_gen stop. 0: tx mixer and quad_gen operate. [0] not used. when idleb = low, minimum bias current is maintained by stopping all the tx circuit functions. to use the above tx puncture function, the external control pin paon must be at low, and the idleb register bit must be at high. if paon is high, it does not respond to the px_pwr register contents.
s1m8657 tx if /bba with agc 30 graph 10 100 1k 10k 100k 1m -120 phase noise(dbc/hz) -110 -100 -90 -80 -70 -60 -50 -40 -30 frequency offset(hz) grph 3-1 s1m8657x01 vco open loop phase noise vcntl(v) 0 -20 -60 -80 -100 -40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output power(dbm) 75 65 55 45 35 25 rs=3.3k acpr2 po acpr1 for cdma full-scale input. grph 3-2 s1m8657x01 output power, acpr vs. vcntl performance grph 3 - 1 s1m8657 vco open loop phase noise grph 3 - 2 s1m8657 output power, acpr vs. vcntl performance for cdma full-scale input for cdma full-scale input. -25 0 +25 +50 +75 -50 +100 temperture(c) output variation(db) -1 0 +1 rs=3.3k/po=-6dbm grph 3-3 s1m8657x01 output variation vs. temperature rs=3.3k/pdm=3.3v -10 -20 -30 -40 -50 -80 -70 -60 snr band-1(dbc/hz) 115 105 95 85 75 65 55 45 0 lower sideband power(dbm) grph 3-4 s1m8657x01 cdma snr band-1 vs. lower sideband pout. grph 3 - 3 s1m8657 output variation vs. temperature for cdma full-scale input grph 3 - 4 s1m8657 cdma snr band-1 vs. lower sideband pout.
tx if/bba with agc s1m8657 31 -10 -20 -30 -40 -50 -80 -70 -60 115 0 110 105 100 95 90 85 80 rs=3.3k/pdm=3.3v snr-1(db) output power(dbm) grph 3-6 s1m8657x01 cdma snr band-1, 1.98m to 44mhz offset. -10 -20 -30 -40 -50 -80 -70 -60 115 0 110 105 100 95 90 85 80 rs=3.3k/pdm=3.3v snr-1(db) output power(dbm) grph 3-5 s1m8657x01 cdma snr band-1, 100k to 1.98mhz offset. grph 3 - 6 s1m8657 cdma snr band-1, 1 . 9 8 m to 4 4 mhz offset grph 3 - 5 s1m8657 cdma snr band-1, 1 0 0 k to 1 . 9 8 mhz offset
s1m8657 tx if /bba with agc 32 test circuit 35 36 33 34 31 32 29 30 27 28 25 26 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 47 48 45 46 43 44 41 42 39 40 37 38 s1m8657 vcc 10nf 10nf 10nf 10nf 1nf 1nf vcoin tclk gpclk gpdata gpena in1 in2 in3 tpll sw_gp gpin sw_msb r=22k sw_sen sw_fm sw_idl sw_lsb clk stb data spi_port 1nf tlock tcxoin 10k tpdset sw_pdst 10k 39k tpdo 10nf tfmod 1nf 10k 1sv229 10k 10k 10k 1.8k vcen sw_pdo 2.2uf 0.033uf 4pf 47pf tvco 10nf 10nf 1nf 1:8 7pf 7pf 1k 1nf 2.3nh 1uf 0.5k 3.3uh 0.5k 3.3uh 10nf 47pf tif_mon sw_vco txd7 txd6 txd5 txd4 txd3 txd2 txd1 txd0 tclkb
tx if/bba with agc s1m8657 33 48bcc pkg outline 7.00 + 0.10 0.085??0.040 stan off 0.80 max total height side view #1 index laser mark top view #1 #13 #25 #37 7.00 + 0.10 7.00 + 0.10 #13 #25 #37 #1 c0.2 0.40 + 0.10 0.50 typ 0.30 + 0.10 0.045 + 0.10 0.045 + 0.10 0.045 + 0.10 0.045 + 0.10 6.15 typ 6.15 typ 6.15 typ 5.0 typ bottom view 5.0 typ 6.15 typ
s1m8657 tx if /bba with agc 34 pkg dimension 48lqfp pkg outline #48 7.00 + 0.20 9.00 + 0.30 7.00 + 0.20 9.00 + 0.30 0.10 max 0.127 + 0.10 - 0.05 0-8 note : dimensions are in millimeters. #1 0.18 + 0.10 - 0.05 0.50 0.08 max (0.75) 0.50 - 0.20 0.05 min 1.40 + 0.10 1.60 max

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